1. Field of the Invention
This invention relates to testing memory components, and in particular, to testing a memory scheme and the memory itself in a dual purpose FIFO/RAM implementation.
2. Description of the Related Art
It is a problem in the field of high-performance, low-cost graphics accelerator circuits used in three-dimensional imaging devices, to verify the circuit's reliability by thoroughly testing memory used in the circuit. Key to testing memory includes, but is not limited to, manipulating the memory in a manner consistent with the implemented memory scheme while testing for anomalies caused by the memory itself. The purpose of testing memory is to verify that the memory scheme and the memory itself operate within acceptable fault parameters.
Testing the memory itself involves testing the ability to store data without the data being lost or corrupted due to a flaw in the electronics or the materials upon which the memory is based. More specifically, due to increasingly complex and miniaturized memory being integrated into electronic circuits, testing horizontally and vertically adjacent memory locations for field overflow is paramount. Field overflow occurs where adjacent bits in a dielectric influence each other due to inadequate insulating properties in the dielectric for the spacing provided between bits. Field overflow results in an unstable memory that corrupts data thereby rendering the memory unreliable.
Testing a memory scheme in a manner consistent with its implementation is a routine process where an ordinary memory scheme is involved. However, in architectures subject to severe circuit space constraints, it is increasingly desirable to implement a hybrid memory scheme to maximize memory use. For example, if a single memory could be used either as a First In First Out (FIFO) memory or as a Random Access Memory (RAM) scheme as needed, a significant circuit space savings could be realized. Unfortunately, such a hybrid memory scheme presents unique problems if circuit design space constraints allow for only minimal test circuitry. Additional problems are created if the FIFO scheme used in the hybrid memory scheme writes successive data units that include data fields each having different field widths.
For example, in the graphics accelerator in which the present invention was developed, a FIFO scheme writes a data unit comprising a partial field width hardware address and a full field width data field in two adjacent memory locations that are each a full field width wide. This makes testing for field overflow difficult if the FIFO scheme is tested in a manner consistent with the implementation. Complicating the testing is the fact that the memory is used as a hybrid FIFO/RAM that uses all available memory locations when functioning as a RAM and only a subset of the available memory locations when functioning as a FIFO.
To fully test a traditional RAM scheme requires a complex test design that writes and reads specific memory test patterns. Further, because testing memory involves field overflow testing, specific patterns must be written to specific memory locations in the RAM.
Testing a traditional FIFO scheme is typically accomplished by writing successive data fields having a common field width into adjacent memory locations, and then reading the data fields in the order written. Identifying a memory location to write to and read from is accomplished by an incremented write/read address pointer. However, if the FIFO scheme writes successive data units comprising multiple data fields each having different fixed field widths, testing memory for field overflow is more complicated due to the memory fragmentation from unused memory locations.
Because the RAM scheme utilizes all memory locations and the FIFO scheme requires only a subset of the memory in different fixed field widths, neither of the traditional FIFO or RAM testing designs are well suited for testing a memory that uses a hybrid RAM/FIFO memory scheme. Therefore, traditional test designs fail to test all memory locations in a memory that is based on a hybrid RAM/FIFO memory scheme, and a solution to this problem is desirable. The existing need for a hybrid RAM/FIFO memory scheme test design has heretofore not been satisfied.